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1 features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) 128-byte page mode only for write operations low-voltage and standard-voltage operation ? 5.0 (v cc = 4.5v to 5.5v) ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 3.6v) 10 mhz (5v), 5mhz (2.7v) and 2 mhz (1.8v) clock rate block write protection ? protect 1/4, 1/2, or entire array write protect (wp ) pin and write disable instructions for both hardware and software data protection high reliability ? endurance: 100k write cycles ? data retention: >40 years 8-pin pdip, 8-lead eiaj soic, 16-lead jedec soic and 8-lead leadless array package description the at25hp256/512 provides 262,144/524,288 bits of serial electrically erasable pro- grammable read only memory (eeprom) organized as 32,768/65,536 words of 8-bits each. the device is optimized for use in many industrial and commercial applications where high-speed, low-power, and low-voltage operation are essential. the at25hp256/512 is available in a space saving 8-pin pdip (at25hp256/512), 8-lead eiaj soic (at25hp256), 16-lead jedec soic (at25hp512) and 8-lead leadless rev. 1113d?05/01 spi serial eeproms 256k (32,768 x 8) 512k (65,536 x 8) at25hp256 at25hp512 pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input (continued) 8-lead soic cs sck so wp hold gnd vcc 1 2 3 4 8 7 6 5 si 8-pin pdip cs sck so wp hold gnd vcc 1 2 3 4 8 7 6 5 si 8-lead leadless array bottom view 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd 16-lead soic 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 cs so nc nc nc nc wp gnd vcc hold nc nc nc nc sck si
at25hp256/512 2 array (at25hp256/512) packages. in addition, the entire family is available in 5.0v (4.5v to 5.5v), 2.7v (2.7v to 5.5v), and 1.8v (1.8v to 3.6v) versions. the at25hp256/512 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self- timed, and no separate erase cycle is required before write. block write protection is enabled by programming the status register with top ? , top ? or entire array of write pro- tection. separate program enable and program disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to pro- tect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. block diagram absolute maximum ratings* operating temperature.................................. -40 c to +125 c *notice: stresses beyond those listed under ? absolute maxi- mum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma 32,768/65,536 x 8
at25hp256/512 3 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v dc characteristics applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +1.8v to +5.5v, t ac = 0 c to +70 c, v cc = +1.8v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max units v cc1 supply voltage 1.8 3.6 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 5 mhz, so = open read 6.0 10.0 ma i cc2 supply current v cc = 5.0v at 5 mhz, so = open write 4.0 7.0 ma i sb1 standby current v cc = 1.8v, cs = v cc 0.1 2.0 a i sb2 standby current v cc = 2.7v, cs = v cc 0.2 2.0 a i sb3 standby current v cc = 5.0v, cs = v cc 2.0 5.0 a i il input leakage v in = 0v to v cc -3.0 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c -3.0 3.0 a v il (1) input low voltage -0.6 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 4.5v v cc = 5.5v i ol = 3.0 ma 0.4 v v oh1 output high voltage i oh = -1.6 ma v cc - 0.8 v v ol2 output low voltage 1.8v v cc = 3.6v i ol = 0.15 ma 0.2 v v oh2 output high voltage i oh = -100 a v cc - 0.2 v
at25hp256/512 4 ac characteristics applicable over recommended operating range from t a = -40 c to +85 c, v cc = as specified, c l = 1 ttl gate and 30 pf (unless otherwise noted). symbol parameter voltage min max units f sck sck clock frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 10 5 2 mhz t ri input rise time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 s t fi input fall time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 s t wh sck high time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 40 80 200 ns t wl sck low time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 40 80 200 ns t cs cs high time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 100 250 ns t css cs setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 100 250 ns t csh cs hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 100 250 ns t su data in setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 12 20 50 ns t h data in hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 10 20 50 ns t hd hold setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 25 50 100 ns t cd hold hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 25 50 100 ns t v output valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 40 80 200 ns t ho output hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 ns
at25hp256/512 5 note: 1. this parameter is characterized and is not 100% tested. t lz hold to output low z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 100 200 300 ns t hz hold to output high z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 300 ns t dis output disable time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 250 ns t wc write cycle time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 10 10 10 ms endurance (1) 5.0v, 25 c, page mode 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100k write cycles ac characteristics (continued) applicable over recommended operating range from t a = -40 c to +85 c, v cc = as specified, c l = 1 ttl gate and 30 pf (unless otherwise noted). symbol parameter voltage min max units
at25hp256/512 6 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25hp256/512 always operates as a slave. transmitter/receiver: the at25hp256/512 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25hp256/512, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25hp256/512 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25hp256/512. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ? 1 ? , all write opera- tions to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status regis- ter. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ? 0 ? . this will allow the user to install the at25hp256/512 in a system with the wp pin tied to ground and still be able to write to the status reg- ister. all wp pin functions are enabled when the wpen bit is set to ? 1 ? . spi serial interface at25hp256/512
at25hp256/512 7 functional description the at25hp256/512 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25hp256/512 utilizes an 8-bit instruction register. the list of instructions and their operation codes are con- tained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. write enable (wren): the device will power up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is independent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. write status register (wrsr): the wrsr instruc- tion allows the user to select one of four levels of protection. the at25hp256/512 is divided into four array segments. top quarter (1/4), top half (1/2), or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status reg- ister control bits are shown in table 4. the three bits, bp0, bp1, and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enable (wpen) bit. hardware write protec- tion is enabled when the wp pin is low and the wpen bit is ? 1 ? . hardware write protection is disabled when either the wp pin is high or the wpen bit is ? 0. ? when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are disabled. writes are only allowed to sections of the memory which are not block-protected. table 1. instruction set for the at25hp256/512 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy table 3. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1= 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 4. bit 3 (bp1) see table 4. bits 4-6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 5. bits 0-7 are 1s during an internal write cycle. table 4. block write protect bits level status register bits array addresses protected bp1 bp0 at25hp256/512 0 0 0 none 1(1/4) 0 1 6000 - 7fff/c000 - ffff 2(1/2) 1 0 4000 - 7fff/8000 - ffff 3(all) 1 1 0000 - 7fff/0000 - ffff
at25hp256/512 8 note: when the wpen bit is hardware write protected, it cannot be changed back to ? 0 ? , as long as the wp pin is held low. read sequence (read): reading the at25hp256/512 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (refer to table 6). upon completion, any data on the si line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the at25hp256/512, two separate instructions must be exe- cuted. first, the device must be write enabled via the write enable (wren) instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all com- mands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address and the data (d7-d0) to be programmed (refer to table 6). programming will start after the cs pin is brought high. (the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruc- tion. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read status register instruction is enabled during the write pro- gramming cycle. the at25hp256/512 is capable of a 128-byte page write operation. after each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 128-bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the at25hp256/512 is automatically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. note: 128-byte page write operation only . content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte write is not supported). table 5. wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable table 6. address key address at25hp256/512 a n a 14 - a 0 / a 15 - a 0 don ? t care bits a 15 / none
at25hp256/512 9 timing diagrams (for spi mode 0 (0,0)) synchronous data timing wren timing wrdi timing so v oh v ol hi- z hi-z si v ih v il skc v ih v il cs v ih v il valid in t css t su t h t wh t wl t v t cs t csh t dis t ho sck cs si so cs sck si so hi-z wrdi op-code
at25hp256/512 10 rdsr timing wrsr timing read timing cs sck 01234567891011121314 si instruction so 76543210 dat a out msb high imped ance
at25hp256/512 11 write timing (at25hp256) sck si so cs 0 1 234 5 67891011202122 23 24 25 26 instruction high impedance byte address 15 14 13 3 2 10 7 65 4 32 1 0 1st byte data in 27 28 29 30 31 ...
at25hp256/512 12 page write timing (at25hp512) hold timing 1043 1044 1045 1046 1047 sck si so cs 0 1 234 5 67891011202122 23 24 25 26 instruction high impedance byte address 15 14 13 3 2 10 7 65 4 32 1 0 128 th byte data in 12 1 st byte data in so sck ho ld cs t cd t hd t hz t hd t cd t lz
at25hp256/512 13 at25hp256 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 10 10000 5.0 10000 at25hp256-10cc at25hp256c1-10cc at25hp256-10pc at25hp256w-10sc 8c 8c1 8p3 8s2 commercial (0 c to 70 c) 10000 5.0 10000 at25hp256-10ci at25hp256c1-10ci at25hp256-10pi at25hp256w-10si 8c 8c1 8p3 8s2 industrial (-40 c to 85 c) 10 4000 2.0 5000 at25hp256-10cc-2.7 at25hp256c1-10cc-2.7 at25hp256-10pc-2.7 at25hp256w-10sc-2.7 8c 8c1 8p3 8s2 commercial (0 c to 70 c) 4000 2.0 5000 at25hp256-10ci-2.7 at25hp256c1-10ci-2.7 at25hp256-10pi-2.7 at25hp256w-10si-2.7 8c 8c1 8p3 8s2 industrial (-40 c to 85 c) 10 3000 2.0 2000 at25hp256-10cc-1.8 at25hp256c1-10cc-1.8 at25hp256-10pc-1.8 at25hp256w-10sc-1.8 8c 8c1 8p3 8s2 commercial (0 c to 70 c) 3000 2.0 2000 at25hp256-10ci-1.8 at25hp256c1-10ci-1.8 at25hp256-10pi-1.8 at25hp256w-10si-1.8 8c 8c1 8p3 8s2 industrial (-40 c to 85 c) package type 8c 8-lead, 0.230" wide, leadless array package (lap) 8c1 8-lead, 0.300" wide, leadless array package (lap) 8p3 8-pin, 0.300" wide, plastic dual in-line package (pdip) 8s2 8-lead, 0.300" wide, plastic gull wing small outline package (eiaj soic) options blank standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 3.6v)
at25hp256/512 14 at25hp512 ordering information t wc (max) (ms) i cc (max) (a) i sb (max) (a) f max (khz) ordering code package operation range 10 10000 5.0 10000 at25hp512-10cc at25hp512c1-10cc at25hp512-10pc at25hp512w2-10sc 8c 8c1 8p3 16s2 commercial (0 c to 70 c) 10000 5.0 10000 at25hp512-10ci at25hp512c1-10ci at25hp512-10pi at25hp512w2-10si 8c 8c1 8p3 16s2 industrial (-40 c to 85 c) 10 4000 2.0 5000 at25hp512-10cc-2.7 at25hp512c1-10cc-2.7 at25hp512-10pc-2.7 at25hp512w2-10sc-2.7 8c 8c1 8p3 16s2 commercial (0 c to 70 c) 4000 2.0 5000 at25hp512-10ci-2.7 at25hp512c1-10ci-2.7 at25hp512-10pi-2.7 at25hp512w2-10si-2.7 8c 8c1 8p3 16s2 industrial (-40 c to 85 c) 10 3000 2.0 2000 at25hp512-10cc-1.8 at25hp512c1-10cc-1.8 at25hp512-10pc-1.8 at25hp512w2-10sc-1.8 8c 8c1 8p3 16s2 commercial (0 c to 70 c) 3000 2.0 2000 at25hp512-10ci-1.8 at25hp512c1-10ci-1.8 at25hp512-10pi-1.8 at25hp512w2-10si-1.8 8c 8c1 8p3 16s2 industrial (-40 c to 85 c) package type 8c 8-lead, 0.230" wide, leadless array package (lap) 8c1 8-lead, 0.300" wide, leadless array package (lap) 8p3 8-pin, 0.300" wide, plastic dual in-line package (pdip) 16s2 16-lead, 0.300" wide, plastic gull wing small outline package (jedec soic) options blank standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 3.6v)
at25hp256/512 15 packaging information 5.03 (0.198) 4.83 (0.190) 6.09 (0.240) 5.89 (0.232) 0.38 (0.015) 0.30 (0.012) 1.14 (0.045) 0.94 (0.037) 0.61 (0.024) 0.51 (0.020) 0.61 (0.024) 0.51 (0.020) 0.89 (0.035) 0.79 (0.031) 1.19 (0.047) 1.09 (0.043) 1.32 (0.052) 1.22 (0.048) 1 2 3 4 8 7 6 5 top view side view bottom view 5.10 (0.201) 4.90 (0.193) 8.10 (0.319) 7.90 (0.311) 0.38 (0.015) 0.30 (0.012) 1.14 (0.045) 0.94 (0.037) 4.76 (0.187) 4.66 (0.183) 0.34 (0.013) 0.24 (0.009) 0.95 (0.037) 0.85 (0.033) 0.92 (0.036) 0.82 (0.032) 1.22 (0.048) 1.12 (0.044) 1 2 3 4 8 7 6 5 top view side view bottom view 1.32 (0.052) 1.22 (0.048) .400 (10.16) .355 (9.02) pin 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) .300 (7.62) ref .210 (5.33) max seating plane .100 (2.54) bsc .015 (.380) min .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62) 0 15 ref .430 (10.9) max .012 (.305) .008 (.203) .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) pin 1 .050 (1.27) bsc .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 0 8 ref .010 (.254) .007 (.178) .035 (.889) .020 (.508) 8c , 8-lead, 0.230" wide, leadless array package (lap) dimensions in inches and (millimeters) 8c1 , 8-lead, 0.300" wide, leadless array package (lap) dimensions in inches and (millimeters) 8p3 , 8-lead, 0.300" wide, plastic dual in-line package (pdip) dimensions in inches and (millimeters) jedec standard ms-001 ba 8s2 , 8-lead, 0.200" wide, plastic gull wing small outline (eiaj soic) dimensions in inches and (millimeters)
at25hp256/512 16 packaging information 0.299 (7.60) 0.291 (7.39) 0.020 (0.508) 0.013 (0.330) 0.420 (10.7) 0.393 (9.98) pin 1 0.050 (1.27) bsc 0.394 (10.00) 0.386 (09.80) 0.012 (0.305) 0.003 (0.076) 0.105 (2.67) 0.092 (2.34) 0 8 ref 0.035 (0.889) 0.015 (0.381) 0.013 (0.330) 0.009 (0.229) 16s2, 16-lead, 0.300" wide, plastic gull wing small outline package (jedec soic)
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